1st NEI WORKSHOP ON DESIGN OF CMOS
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December 19-29, 2011 | ||||
Organized by | ||||
Network of Engineering Institutions (NEI) | ||||
A consortium of four premier institutes : LNMIIT, Jaipur; DA-IICT, Gandhinagar; MITS,Sikar | ||||
Hosted by | ||||
The LNM Institute of Information Technology (LNMIIT), Jaipur | ||||
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Introduction :The Network of Engineering Institutions (NEI) has been founded with a collaborative effort of the participating institutions to promote cutting edge research in the field of VLSI for achieving indigenous chip designing and fabrication capabilities in India. The cooperative research program envisages a network of engineering colleges, universities and other institutes coupled to a networked panel of experts, who would be responsible for continuous monitoring and guidance of the research program. To promote the idea, every year NEI will organize two workshops on specialized branches of VLSI design and semiconductor technology. The first workshop in this series will be held at The LNM Institute of Information Technology, Jaipur during Dec. 19-29, 2011. This short term workshop will offer, along with stimulating lectures by renowned experts in this area, a rare opportunity to gather hands-on experience in designing of CMOS analog circuits. The program will also provide a forum for professional interaction between VLSI experts, faculties, researchers, and students, which would hopefully lead to useful research collaboration amongst the participating institutions in due course of time. Course Contents :1. Physics of Semiconductor Devices (12 Contact hours) : Band theory, Continuity equation, P-N junction : zero and reverse bias, forward bias, capacitance, Metal-semiconductor contacts, MOS capacitor, BJTs & MOSFETs. 2. CMOS Analog Circuit Design (49 Contact hours : Theory 28 hours, Lab 21 hours) : The main objective of this course is to learn how to analyze and design CMOS analog amplifier circuits. The emphasis will be on circuit design, and in every phase of the course, the learner will be expected to design, on paper as well as in simulation, the circuits discussed in the lectures. This course will broadly cover the following topics : 3. Laboratory Project (5 hours) : Design of PLL, ADC, etc. The main objective of this course is to learn how to analyze and design CMOS analog amplifier circuits. The emphasis will be on circuit design, and in every phase of the course, the learner will be expected to design, on paper as well as in simulation, the circuits discussed in the lectures. This course will broadly cover the following topics : Evaluation Scheme:Participants interested in grading will be evaluated through regular exams. Those participants will have to do a separate registration (on spot) with an additional registration fee of Rs. 3000 (over and above the workshop fee). This evaluation scheme is completely optional. Participation certificates will be provided to all the participants. Faculties and participants from industry will remain outside the evaluation scheme. Speakers and Lab Facilitators (confirmed) :Prof. R. Sharan (Distinguished Professor, LNMIIT, Ex-professor, IIT Kanpur) Who can attend :The workshop will be useful for PhD scholars, and MS/MTech/MSc/BTech students, who are interested in enriching their knowledge in VLSI design. Faculties from engineering colleges/technical institutions/universities will find the program very useful for teaching CMOS analog circuit design and Solid state devices. The program will also be helpful for executives and engineers from industry who wants to have a flavour of modern trends in CMOS analog circuit design. |
Workshop Fees :1. PhD/MS/MTech students : Rs. 10000 (with accommodation), Rs. 8500 (without accommodation) 2. BTech/MSc students : Rs. 6500 (with accommodation), Rs. 5000 (without accommodation) 3. Faculties : Rs. 12,000 (with accommodation), Rs. 10500 (without accommodation) 4. Industry participants : Rs. 25,000 (without accommodation). Accommodation can be arranged in hotels on request only. Faculties, research scholars and students belonging to the four NEI participating institutions are eligible for a fee waiver up to an extent. For details, kindly contact the convenor or the NEI executive committee members of your institute. Food and Accommodation :Food (breakfast, lunch and dinner) will be provided to all the participants. The workshop fee includes the cost of food. Accommodation will be provided in student hostels. Participants from nearby areas, who do not want to avail accommodation facility, will be provided daily conveyance from specific locations in Jaipur city. Traveling Allowance :No TA will be provided to the participants. How to apply :Filled in registration form (attached herewith or a copy of it or downloaded from the link: www.lnmiit.ac.in/NEI Workshop 2011 ) along with the aforementioned fee in the form of DD in favour of The LNM Institute of Information Technology, payable at Jaipur, should reach the Convenor on or before Dec. 10, 2011. Kindly use EMS Speed Post service only for sending the documents. Contact :Address of Convenor:Dr. Somnath Biswas For other queries please contact :
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