Department of Electronics & Communication Engineering

The LNM Institute of Information Technology

Mr. Kapil Jainwal

Personal Information
Name Mr. Kapil Jainwal
Designation Assistant Professor
Department Electronics & Communication Engineering
URL
Date of Joining -
Contact Information
Address Room no 151, Department of Electronics & Communication Engineering, The LNM Institute of Information Technology, Jaipur - 302031
City JAIPUR
State RAJASTHAN
Country INDIA
Email Address kapil.jainwal@lnmiit.ac.in
Phone [Mobile] 9783148133
Office Extention 1207
Academic Information
Degree/Diploma Institute/ Organization Year Branch/Specialization
1 B.E.  ( Bachelor of Engineering ) SGSITS Indore 2005 Electronics and Instrumentation
2 M. Tech.  ( Master of Technology ) Indian Institute of Technology (IIT) -Bombay 2008 Electronic System - VLSI Design
3 Ph. D.  ( Doctor of Philosophy ) Pursuing from Electrical Department (IC Design), Indian Institute of Technology (IIT) –Delhi 2013 Analogue/ Mixed mode Circuits, CMOS Image sensors
Research Publications
 
1 Chandani anand, Kapil Jainwal, and M. Sarkar, "A High Background Light Subtraction Circuit for Long Range Time-of- Flight Cameras", IEEE Asia Pacific Conference on Circuits & Systems (APCCAS), Jeju, Korea, Oct. 2016    OCT  2016      


2 Vivek Sharma, Kapil Jainwal, Nithin Kumar Y.B., Vasantha M.H, and Abhishek Tripathi, "Design of a Hybrid Ring Oscillator at 1.5/3.0 GHz with Low Power Supply Sensitivity", IEEE Asia Pacific Conference on Circuits & Systems (APCCAS), Jeju, Korea, Oct. 2016    OCT  2016      


3 Kapil Jainwal, Kushal Shah and Mukul Sarkar, “Low Frequency Noise Reduction using Multiple Transistors with Variable Duty Cycle Switched Biasing”, IEEE Journal of Electron Device Society. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7225100&newsearch=true&queryText=kapil%20jainwal    AUG  2015      


4 G.K. Reddy, Kapil Jainwal and Jawar Singh, “Process variation tolerant 9T SRAM bitcell design”, IEEE 13th International Symposium on Quality Electronic Design (ISQED), Santa Clara, California, USA. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6187539&newsearch=true&queryText=kapil%20jainwal    MAR  2012      


5 Kapil Jainwal and Jayanta Mukherjee, “Phase noise reduction in CMOS LC oscillators using tail noise shaping and Gm3 boosting”, IEEE International Conference on Electrical and Computer Engineering. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4769221&newsearch=true&queryText=kapil%20jainwal    DEC  2008      


Academic Experience
 
Name of Institute Duration From Duration To
1 Jaypee University of Engineering and Technology 2009 2012
2 The LNMIIT, Jaipur 2013 2016
Industrial Experience
 
Name of Industry Duration From Duration To
1 Dar Al-Handasah (Shair and Partners), Pune 2008 2009